| The Novel Solution |
An approach was pursued which augments timed
break triggering with additional "smarts" to track break timing variances. A
pause detector was developed that senses absence of audible audio, and signals the
automation system when the duration exceeds seven-tenths of a second. The pause
detector had to provide a reliable output signal to the automation system,
cue-tone-detector style, and although simple silence sensors exist for detecting
automation system failure, they had not been adapted for this purpose. The circuit design
goal was to prevent transition during detectable audible program material, and we
took several steps to design-in high reliability to prevent false triggering.
First, the threshold of audibility detection was carefully controlled. The sensitivity
of the unit is augmented by shaping the frequency response to emulate human hearing. Using
the well-known Fletcher and Munson response curves (see our quick sidebar explanation on Fletcher-Munson curves),
we modeled the weighting factor after the mid-level intensity curve, realizing that most
listeners would have their receivers somewhere at this level or lower.
Second, since it’s also known that quick pulses of frequencies normally audible
will not generally be heard if they are brief enough, the attack time of the level
detector was tailored to approximate the DIN standard 45406 for peak program meters which
describes this effect. Thus, "blurts" of sound will not falsely inhibit the
pause trigger.
Under normal conditions with a perfectly clean one (or even two) second break, the
above frequency response tailoring and attack time control are not necessary. But to make
the circuit maximally robust, and able to cope with background noises, such as paper
shuffling, these refinements had to be built in.
The "inaudible silence" or pause must last at least 700
milliseconds (0.7 Seconds) to be considered a "valid" break, and if any sounds
pass through the filters during this time, it is reasonable to believe the audience would
hear the sounds too, and the timing circuit is reset to wait for another "inaudible
silence". In the case of too short a break (600 ms), if the attack (timer reset) time
were 100 ms, the break would still be triggered with clipped audio.The Pause Detector
Timings & Breaks illustration (above) depicts graphically the timing
relationships. 
Figure 3 is a full-size (84.9K jpeg)
schematic of the circuit. (click on the thumbnail graphic, left, to see
the entire schematic in a new window. The circuit description follows below).
A Description of the Pause
Detector Circuit
(See the full-size schematic,
if you haven't already done so.)
A four-section LM324
Operational Amplifier is the heart of the circuit, and performs these tasks:
1. The Input Differential Amplifier
2. The Filter-Detector
3. Timer
4. Peak Comparator
Also see (below): Inhibiting the
Pause Detector output | Power supply requirements.
 The input differential
amplifier is biased to half supply (+9 volts) by R4 and R5, and converts a
balanced line level input (0 dBm to +8 dBm) to a single ended usable level. Slight high
pass filtering is provided by C3 and C4, which also block dc offset.
Below unity-gain operation is achieved to allow the upper 30 dB of program dynamic range
to be compared. The output is AC coupled into a bandpass network that rolls off above 5KHZ
and slowly rolls off frequencies below 500Hz.
The right PC trimpot VRl, controls detector input gain, with the center position
approximately correct for +8 dBm line level.
The
detector is biased at silicon junction voltage by D1. The output is rectified by
D2, which also removes most quiescent dc. The combination of the reactive input components
and the feedback network in the first two stages (C3, C4,
C5, C6, C8, C9, and C10) forms the
bandpass filtering approximating middle-intensity (60dB to 70dB) Fletcher & Munson response.
Seven-tenths of a volt output is the threshold for both the green (level present) LED and
the timer reset, achieved simply with NPN transistor junctions.
The timer section
compares the charge on C12 against a resistor-network-derived reference voltage, feeding
the open-collector style "Pause out" port through a red LED. The left PC board trimpot (VR2) sets the charging rate of C12. When
centered, the time constant should be approximately 700 milliseconds.
A second Comparator
forms the peak level indicator (yellow LED) which should blink on
normal-level program peaks.
Should it be necessary to inhibit
the output, a relay or transistor closure applied to the mute input prevents the
LED and transistor from coming on. This outboard closure should be able to sink 20
milliamps.
Power supplied to the circuit
should be well filtered +12 to +16 volts dc, with a maximum current of 60 milliamps. In
high RF environments, a shielded enclosure and bypassed port connections are recommended.
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